The present invention generally relates to communication systems, and, more particularly, to a communication system having a communication controller and multiple physical interfaces, and to a method.
In many communication systems, a physical interface (e.g., a xe2x80x9cPHYxe2x80x9d, or xe2x80x9cphysical layer devicexe2x80x9d) connects a communication channel (e.g., fiber optic line, phone line, radio link) to a communication processor. For example, the system operates in the Asynchronous Transfer Mode (ATM) in which the channels transfer data in cells (e.g., blocks of bytes). In such cases, the communication processor (xe2x80x9cATM layer unitxe2x80x9d) can be either a cell processor or a Segmentation and Reassembly (SAR) unit. Preferably, a single processor can serve multiple (e.g., n) PHYs. In the terms of ATM, processor, PHYs and channels belong to the so-called physical layer. Many references are dedicated to ATM, such as [1] Reif O. Onvural: xe2x80x9cAsynchronous Transfer Mode, Performance Issuesxe2x80x9d, Second Edition, Artech House Boston and London, 1995, ISBN 0-89006-804-6, especially chapter 2.4 xe2x80x9cPhysical Layerxe2x80x9d; [2] The ATM Forum, Technical Committee: xe2x80x9cUtopia Level 2, Version 1.0xe2x80x9d, June 1995, [FIG. 2.3B with a single ATM (communication processor) and multiple PHYs]; [3] U.S. Pat. No. 5,485,456 to Shtayer et al.; and [4] U.S. Pat. No. 5,418,786 to Loyer et al.
Coupling multiple PHYs to a single ATM layer can require additional pins to the processor and packages which is not desirable. The present invention seeks to provide systems which mitigate or avoid these and other disadvantages and limitations of the prior art.